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NEW QUESTION: 1
What involves creating a visual depiction of a process, is the starting point to help understand each process and identify the sequencing of each process?
A. Process Equipment
B. Process Planning
C. Process mapping
D. Process flowcharting
Answer: C

NEW QUESTION: 2
최고 경영자 (CEO)는 주요 경쟁사가 새로운 캠페인을 계획하고 있다고 생각합니다. CEO는 새로운 캠페인이 무엇인지에 대한 독창적 사고를 요구하는 설문지를 주요 직원에게 보냅니다. CEO는 최선의 가능성을 선택한 다음 가장 가능성있는 옵션을 요구하는 다른 설문지를 보냅니다. CEO가 채택한 프로세스를
A. 예상 보수 최적화.
B. 델파이 기술.
C. 최대 가능성 기술.
D. 최소 제곱 기술.
Answer: B
Explanation:
The Delphi technique is a forecasting or decision-making approach that attempts to avoid groupthink the tendency of individuals to conform to what they perceive to be the consensus). The technique allows only written, anonymous communication among group members. Each member takes a position on the problem at hand. A summary of these positions is communicated to each member. The process is repeated for several iterations as the members more toward a consensus. Thus, the Delphi technique is a qualitative, not quantitative, technique. The College Honor Society sells hot pretzels at the home football games. The pretzels are sold for US $1.00 each, and the cost per pretzel is U $.30. Any unsold pretzels are discarded because they will be stale before the next home game. 95. The estimated demand for pretzel at the next home football game.

NEW QUESTION: 3
Hotspot Question
Match each technology to its description.


Answer:
Explanation:

http://h71000.www7.hp.com/doc/83final/b9073_90111/apas13.html
The LPMC monitor, within the Support Tools Manager (STM) diagnostics, generates Information events for all cache errors that are detected. After three errors (Threshold) have been detected on a processor in 1440 minutes, or a 24-hour period of time (Period), the monitor deactivates that particular processor, marks it for deconfiguration on the next system reboot, and generates a SERIOUS event. After the failed processor is deactivated, the LPMC monitor attempts to activate one of the inactive Instant Capacity processors, if any are available. This method ensures the processing power of the system is unchanged.
A default value of "three" is assigned to Threshold, except for the PCX-W+ family of processors, which has a value of "five" assigned. The default value assigned to a Period is 1440 minutes, or 24 hours, in all possible processor configurations.
An inactive processor under warranty or support automatically replaces a failed processor. HP also services and replaces any failed processor.
http://www.techrepublic.com/whitepapers/mca-error-recovery-hp-ux-feature-for-recovering-frommachinecheck-aborts/354967
HP Integrity servers provide superior reliability and availability. Nevertheless, even the best of computers can occasionally experience hardware problems that lead to unplanned downtime. Some of these problems are caused by transient events such as an alpha particle strike on memory, cache, or a processor data structure.
Intel Itanium-based servers support an advanced architecture that allows the system to contain, correct, and signal machine check errors. Many of these errors are corrected by the platform without operating system intervention. When the platform cannot correct an error, it will be handed off to the operating system. To further enhance the superior reliability of HP Integrity servers, the HP-UX MCA Error Recovery feature adds the ability to recover from some of these Machine Check Aborts (MCAs).
http://dl.acm.org/citation.cfm?id=1057740
Soft errors are functional failures resulting from the latching of single-event transients (transient voltage fluctuations at a logic node or SETs) caused by high-energy particle strikes or electrical noise. Due to technology scaling and reduced supply voltages, they are expected to increase by several orders of magnitude in logic circuits. Both combinational and sequential logic circuits are expected to be affected. Many different latch designs to prevent soft errors due to particle strikes on the latch nodes have been proposed. We review these designs and compare them based on their robustness and their power and performance overheads. We also propose new latch designs, the best of which is vulnerable only to a single-event, multiple-upset without any delay overhead and consumes only 40% power of a standard latch. We expect this work will help
designers to select latches for applications where soft error is an important design metric.
http://en.wikipedia.org/wiki/Montecito_(processor)
Advanced compensation for errors in cache, for reliable operation under mission-critical workloads. This was code-named Pellston technology during development, and has recently been renamed Intel Cache Safe Technology